1. Field of the Invention
Example embodiments relate to a voltage supply circuit and a semiconductor memory device and, more particularly, to a voltage supply circuit and a semiconductor memory device which are capable of quickly raising an operating voltage.
2. Description of the Related Art
A semiconductor memory device requires a plurality of operating voltages (e.g., a program voltage, a read voltage, an erase voltage, and a pass voltage) in a program operation, a read operation, and an erase operation.
An external power source is raised by a pump circuit because the operating voltages are much higher than the external power source.
A pump capacitor occupies most of the area of the pump circuit. The size of the pump capacitor typically depends on a load of an output node. The load of the output node may include a load due to global word lines, a load due to local lines, and a load due to a junction capacitor of a pass transistor within a row decoder corresponding to each memory block.
As the degree of integration of memory devices increases, the number of global word lines is increased and a load caused by the global word lines is also greatly increased. There are two main methods of minimizing global word line loads. The first method is a half string method of reducing a line load. The second method involves reducing a junction capacitor load of a turned-off pass transistor by reducing the number of global word lines coupled to a memory block. Although these are the types of methods that are typically used, the line and junction capacitor loads cannot be greatly reduced and a pass voltage (VPASS) rising time is not greatly reduced.